The invention relates to the fabrication of BIFET monolithic integrated circuit (IC) devices. These ordinarily include a combination of bipolar junction transistor (BJT) devices and junction field effect transistor (JFET) devices manufactured together in a compatible process. Typically, the JFET devices are manufactured using ion implantation in relatively thin structures that can be mass produced with consistent characteristics. If desired, the JFET structure performance can be improved using the approach disclosed in U.S. Pat. No. 4,176,368 which issued Nov. 27, 1979, to the assignee of the present application.
In copending application Ser. No. 153,805 filed May 27, 1980 by Brian E. Hollins and titled BIPOLAR SEMICONDUCTOR PROCESS AND STRUCTURE FOR IMPROVED RELIABILITY, a process is described for making bipolar ICs. When that process is applied to circuits that include thin JFETS, it has been standard practice to apply the process by a masked ion implant operation to the IC process. The JFET devices are then fabricated by masked ion implant operations to create channel and top gate electrodes. The completed IC includes a passivating oxide with conventional metallization thereon, and an overcoat of silicon nitride, deposited by a plasma process, to passivate the structure.